ARM announced a new high-performance cacahe coherent network targeted at energy-efficient ‘many-core’ solutions for the enterprise market.
ARM® CoreLink™ CCN-504 cache coherent network can deliver up to one terabit of usable system bandwidth per second and it will enable SoC designers to provide high-performance, cache coherent interconnect for ‘many-core’ enterprise solutions built using the ARM Cortex™-A15 MPCore™ processor and next-generation 64-bit processors.
ARM has also unveiled the new ARM CoreLink DMC-520 dynamic memory controller that has been designed and optimized to work with the CoreLink CCN-504. The new dynamic memory controller provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. It is part of an integrated ARM DDR4 interface solution incorporating ARM Artisan® DDR4/3 PHY IP planned for introduction in 2013.
Read the whole press release on arm.com