IBM released some specs on Power8 at Hot Chips conference

IBM_power_logoDuring the Hot Chips conference at Stanford University on Monday, IBM representatives showed details of Power8, the motor for the company’s Power Systems lineup.

New features include:

  • shifting from the 32-nanometer processes used for the relatively recent Power7+ chips to a 22-nanometer process
  • integrated PCI-Express 3.0 controllers on the Power8 die provide the transport layer for what IBM is calling the Coherence Attach Processor Interface, or CAPI; this enables direct connect to GPU, FPGAs and other accelerators
  • new cache hierarchy that goes all the way out to the L4 cache
  • 12 cores with 8 SMT
  • generic memory controller on the chip that connects to an external memory buffer, wich can be upgraded with minimum effort to DDR4 when needed
  • eight memory channels, for a total of 230GB/sec of sustained bandwidth

Depending on the workload, a Power8 chip will yield somewhere around 2.5 times the performance as a baseline Power7+ chip, for chips running at 4GHz.

Read a detailed article on The Register.

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