Oracle announced its Next Generation Processor at the HotChips HC26 conference.
The M7 has 32 cores (up from 16-cores in T5 and 12-cores in M6) and is produced with 20 nm technology. It is built using the foundation of the S4 corethat has 8 dynamic threads. It increases the frequency while maintaining the Pipeline depth and each core has its own fine grain power estimator that keeps the core within its power envelop in 250 nano-sec granularity. Each core also includes Software in Silicon features for Application Acceleration Support. Each core includes features to improve Application Data Integrity, with almost no performance loss.
- 16 KB Instruction and 16 KB Data L1 cache/core
- the cores are organized in sets of 4-core clusters that share 256 KB of 4 way set associative L2 cache with over 1/2 TB/s of throughput. Each Two cores share 256 KB of 8 way set associative L2 Data Cache, with over 1/2 TB/s of throughput
- each M7 chip has 8 sets of these core-clustersa and 64 MB on-chip L3 cachewith an aggregate bandwidth of over 1.6TB/s
- 4 DDR4 memory controllers per chip and can support upto 16 DDR4 DIMMs, allowing for 2 TB of RAM/chip
the chip also includes 4 internal links of PCIe Gen3 I/O controllers
- each chip has 7 coherence links, allowing for 8 of these chips to be connected together gluelessly. Also 32 of these chips can be connected in an SMP configuration.
A potential system with 32 chips will have 1024 cores and 8192 threads and 64 TB of RAM